A Pipelined Multi-core MIPS Machine Hardware Implementation by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

This monograph is predicated at the 3rd author's lectures on desktop structure, given in the summertime semester 2013 at Saarland collage, Germany. It features a gate point development of a multi-core computer with pipelined MIPS processor cores and a sequentially constant shared memory.

The booklet comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache established sequentially constant shared reminiscence. This opens find out how to the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and therefore deterministic. by contrast the reference versions opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.

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Extra resources for A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof

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27. If the input yin is 0, then the open collector driver also outputs 0. If the input is 1, then the driver is disabled. In detailed timing diagrams, an undefined value due to disabled outputs is usually drawn as a horizontal line in the middle between 0 and 1. In the jargon of hardware designers this is called the high impedance state or high Z or simply Z. In order to specify behavior and operating conditions of open collector and tristate drivers, we have to permit Z as a signal value for drivers y.

If all the drivers connected to the open collector bus are disabled, then in the physical design a pull-up resistor drives 1 on the bus. The bus value b(t) is then determined as 56 3 Hardware y1 in yk in ··· OC OC yk y1 b Fig. 28. Open collector drivers yi connected by a bus b ⎧ ⎪ ⎨0 b(t) = 1 ⎪ ⎩ Ω ∃i : yi (t) = 0 ∀i : yi (t) = Z otherwise . In the digital model, we simply get bt = yi int , i but this abstracts away an important detail: glitches on a driver input can propagate to the bus, for instance when other drivers are disabled.

16 and compute output yn−1 as yn−1 = xn−1 ◦ yn−2 using one extra ◦-gate. For the correctness of the construction, we first observe that xi = x2i+1 ◦ x2i y2i = x2i ◦ yi−1 y2i+1 = yi . We first show that odd outputs of the circuit satisfy (6). For i = 0 we have y1 = y0 (construction) = x0 (ind. hypothesis P P◦ (n/2)) = x1 ◦ x0 . (construction) For i > 0 we conclude y2i+1 = yi (construction) = xi ◦ yi−1 (ind. hypothesis P P◦ (n/2)) = (x2i+1 ◦ x2i ) ◦ yi−1 (construction) = x2i+1 ◦ (x2i ◦ yi−1 ) (associativity) = x2i+1 ◦ y2i .

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